The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC design and material have produced generations of ICs where each generation has smaller and more complex circuits than previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, high-k (HK) dielectric material and metal gate (MG) are often considered to form a gate stack for a field-effect transistor (FET). Integration issues occur when forming various contacts of source/drain and of MG, especially when film types being etched in source/drain contacts are substantially different than ones in MG contacts. It is desired to have improvements in this area.